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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order Number: MPC9992/D Rev 2, 04/2002
Product Preview 3.3V Differential ECL/PECL PLL Clock Generator
The MPC9992 is a 3.3 V compatible, PLL based PECL clock driver. Using SiGe technology and a fully differential design ensures optimum skew and PLL jitter performance. The performance of the MPC9992 makes the device ideal for workstation, mainframe computer and telecommunication applications. With output frequencies up to 400 MHz and output skews less than 150 ps1 the device meets the needs of the most demanding clock applications. The MPC9992 offers a differential PECL input and a crystal oscillator interface. All control signals are LVCMOS compatible. Features
MPC9992
3.3V DIFFERENTIAL ECL/PECL PLL CLOCK GENERATOR
* 7 differential outputs, PLL based clock generator * SiGe technology supports minimum output skew (max. 150 ps1) * Supports up to two generated output clock frequencies with a maximum
clock frequency up to 400 MHz
* Selectable crystal oscillator interface and PECL compatible clock input * SYNC pulse generation * PECL compatible differential clock inputs and outputs * Single 3.3V (PECL) supply * Ambient temperature range 0C to +70C * Standard 32 lead LQFP package * Pin and function compatible to the MPC992
Functional Description
FA SUFFIX 32 LEAD LQFP PACKAGE CASE 873A
The MPC9992 utilizes PLL technology to frequency lock its outputs onto an input reference clock. The reference clock frequency and the divider for the feedback path determine the VCO frequency. Both must be selected to match the VCO frequency range. The MPC9992 features frequency programmability between the three output banks outputs as well as the output to input relationships. Output frequency ratios of 2:1, 3:1, 3:2 and 5:2 can be realized. The two banks of outputs and the feedback frequency divider can be programmed by the FSEL[2:0] pins of the device. The VCO_SEL pin provides an extended PLL input reference frequency range. The SYNC pulse generator monitors the phase relationship between the QA[3:0] and QB[2:0] output banks. The SYNC generator output signals the coincident edges of the two output banks. This feature is useful for non binary relationships between output frequencies. The REF_SEL pin selects the differential PECL compatible input pair or crystal oscillator interface as the reference clock signal. The PLL_EN control selects the PLL bypass configuration for test and diagnosis. In this configuration, the selected input reference clock is routed directly to the output dividers bypassing the PLL. The PLL bypass is fully static and the minimum clock frequency specification and all other PLL characteristics do not apply. The MPC9992 requires an external reset signal for start-up and for PLL recovery in case the reference input is interrupted. Assertion of the reset signal forces all outputs to the logic low state. The MPC9992 is fully 3.3V compatible and requires no external loop filter components. The differential clock input (PCLK) is PECL compatible and all control inputs accept LVCMOS compatible signals while the outputs provide PECL compatible levels with the capability to drive terminated 50 W transmission lines. The device is pin and function compatible to the MPC992 and is packaged in a 32-lead LQFP package. 1. Final specification of this parameter is pending characterization.
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
(c) Motorola, Inc. 2002
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MPC9992
Bank A QA0 QA0 QA1 QA1 QA2 QA2 QA3 QA3 Bank B VCC VCO_SEL PLL_EN FSEL[1:0] FB QB0 QB0 QB1 QB1 QB2 QB2
2
VCC XTAL_IN XTAL_OUT PCLK PCLK
All input resistors have a value of 50k
XTAL
1 0 Ref VCO /4 /2 1
0 1 0
/2, /4 /4, /6, /10 /16, /24, /40 Sync Pulse
PLL
VCC 800-1600 MHz
REF_SEL
VCC Sync
MR/STOP
QSYNC QSYNC
Figure 1. MPC9992 Logic Diagram
QSYNC QSYNC 18
VCC
24 QA1 QA1 QA0 QA0 GND VCC_PLL MR/STOP VCC 25 26 27 28 29 30 31 32 1
23
22
21
20
19
VCC 17 16 15 14 13 QB0 QB0 QB1 QB1 QB2 QB2 PLL_EN GND 12 11 10 9 8 XTAL_OUT
QA2
QA2
QA3 4
MPC9992
2
3
QA3 5
6
7
VCO_SEL
REF_SEL
Figure 2. MPC9992 32-Lead Package Pinout (Top View)
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XTAL_IN
FSEL0
FSEL1
PCLK
PCLK
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MPC9992
Table 1: MPC9992 PLL Configurations
VCO_SEL 0 0 0 0 1 1 1 1 FSEL_0 0 0 1 1 0 0 1 1 FSEL_1 0 1 0 1 0 1 0 1 fREF (MHz) 16.6-33.3 25-50 10-20 16.6-33.3 8.3-16.6 12.5-25 5-10 8.3-16.6 QA[3:0] (NA) VCO/8 (6 fREF) VCO/4 (8 fREF) VCO/8 (10 fREF) VCO/4 (12 fREF) VCO/16 (6 fREF) VCO/8 (8 fREF) VCO/16 (10 fREF) VCO/8 (12 fREF) QB[2:0] (NB) VCO/12 (4 fREF) VCO/8 (4 fREF) VCO/20 (4 fREF) VCO/12 (4 fREF) VCO/24 (4 fREF) VCO/16 (4 fREF) VCO/40 (4 fREF) VCO/24 (4 fREF) Frequency Ratio QA to QB 3/2 2/1 5/2 3/1 3/2 2/1 5/2 3/1 Internal Feedback (M VCO_SEL) VCO/48 VCO/32 VCO/80 VCO/48 VCO/96 VCO/64 VCO/160 VCO/96
Table 2: FUNCTION TABLE (Configuration Controls)
Control REF_SEL VCO_SEL PLL_EN Default 1 1 1 0 Selects PCLK, PCLK as PLL refererence signal input Selects VCO/2. The VCO frequency is scaled by a factor of 2 (high input frequency range) Test mode with the PLL bypassed. The reference clock is substituted for the internal VCO output. MPC9992 is fully static and no minimum frequency limit applies. All PLL related AC characteristics are not applicable. Normal operation 1 Selects the crystal oscillator as PLL reference signal input Selects VCO/4. The VCO frequency is scaled by a factor of 4 (low input frequency range). Normal operation mode with PLL enabled.
MR/STOP
0
Reset of the device and output disable (output clock stop). The outputs are stopped in logic low state: Qx=L, Qx=H. The minimum reset period should be greater than one reference clock cycle.
VCO_SEL and FSEL[1:0] control the operating PLL frequency range and input/output frequency ratios. See Table 1 for the device frequency configuration.
Table 3: PIN CONFIGURATION
Pin PCLK, PCLK XTAL_IN, XTAL_OUT VCO_SEL PLL_EN REF_SEL MR/STOP FSEL[1:0] QA[0-3], QA[0-3] QB[0-2], QB[0-2] QSYNC, QSYNC GND VCC VCC_PLL Input Input Input Input Input Output Output Output Supply Supply Supply I/O Input Type PECL Analog LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS PECL PECL PECL GND VCC VCC Differential reference clock signal input Crystal oscillator interface VCO operating frequency select PLL Enable/Bypass mode select PLL reference signal input select Device reset and output clock disable (stop in logic low state) Output and PLL feedback frequency divider select Differential clock outputs (bank A) Differential clock outputs (bank B) Differential clock outputs (bank C) Negative power supply Positive power supply. All VCC pins must be connected to the positive power supply for correct DC and AC operation PLL positive power supply (analog power supply). It is recommended to use an external RC filter for the analog power supply pin VCC_PLL. Please see applications section for details Function
TIMING SOLUTIONS
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Table 4: ABSOLUTE MAXIMUM RATINGSa
Symbol VCC VIN VOUT IIN IOUT TS Supply Voltage DC Input Voltage DC Output Voltage DC Input Current DC Output Current Storage Temperature -65 Characteristics Min -0.3 -0.3 -0.3 Max 3.6 VCC+0.3 VCC+0.3 20 50 125 Unit V V V mA mA C Condition
a. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied.
Table 5: GENERAL SPECIFICATIONS
Symbol VTT MM HBM CDM LU CIN JA Characteristics Output termination voltage ESD Protection (Machine model) ESD Protection (Human body model) ESD Protection (Charged device model) Latch-up immunity Input capacitance Thermal resistance junction to ambient JESD 51-3, single layer test board 200 4000 1500 200 4.0 83.1 73.3 68.9 63.8 57.4 59.0 54.4 52.5 50.4 47.8 23.0 86.0 75.4 70.9 65.3 59.6 60.6 55.7 53.8 51.5 48.8 26.3 Min Typ VCC - 2 Max Unit V V V V mA pF C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W Inputs Natural convection 100 ft/min 200 ft/min 400 ft/min 800 ft/min Natural convection 100 ft/min 200 ft/min 400 ft/min 800 ft/min MIL-SPEC 883E Method 1012.1 Condition
JESD 51-6, 2S2P multilayer test board
JC TJ a.
Thermal resistance junction to case Operating junction temperaturea (continuous operation) MTBF = 9.1 years
0
110
C
Operating junction temperature impacts device life time. Maximum continuous operating junction temperature should be selected according to the application life time requirements (See application note AN1545 for more information). The device AC and DC parameters are specified up to 110C junction temperature allowing the MPC9992 to be used in applications requiring industrial temperature range. It is recommended that users of the MPC9992 employ thermal modeling analysis to assist in applying the junction temperature specifications to their particular application.
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MPC9992
Table 6: DC CHARACTERISTICS (VCC = 3.3V 5%, GND = 0V, TA = 0C to 70C)a
Symbol VPP VCMR IIN VIH VIL IIN VOH VOL ICC_PLL IGNDf a. b. c. d. e. f. Characteristics AC differential input voltagec Differential cross point Input Currente Input high voltage Input low voltage Input Currente Output High Voltage Output Low Voltage Maximum PLL Supply Current Maximum Supply Current TBD TBD VCC-1.005 VCC-1.705 2.0 voltaged Min 0.1 1.0 Typ Max 1.3 VCC-0.3 200 VCC + 0.3 0.8 200 TBD TBD 20 150 Unit V V A V V A V V mA mA Condition Differential operation Differential operation VIN=VCC or GND LVCMOS LVCMOS VIN=VCC or GND Termination 50W to VTT Termination 50W to VTT VCC_PLL pin VCC pins Differential PECL clock inputs (PCLK, PCLK)b
Single-ended PECL clock inputs (VCO_SEL, PLL_EN, MR/STOP, REF_SEL, FSEL[1:0])
PECL clock outputs (QA[3:0], QA[3:0], QB[2:0], QB[2:0], QSYNC, QSYNC)
Supply Current
AC characteristics are design targets and pending characterization. Clock inputs driven by PECL compatible signals. VPP is the minimum differential input voltage swing required to maintain AC characteristics. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR (DC) range and the input swing lies within the VPP (DC) specification. Inputs have pull-down resistors affecting the input current. Does not include output drive current which is dependant on output termination methods.
TIMING SOLUTIONS
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MPC9992
Table 7: AC CHARACTERISTICS (VCC = 3.3V 5%, GND = 0V, TA = 0C to +70C)a b
Symbol fref Characteristics Input reference frequency /32 feedback /48 feedback /64 feedback /80 feedback /96 feedback /160 feedback Min 25.0 16.67 12.5 10.0 8.33 5.0 Typ Max 50.0 33.3 25.0 20.0 16.67 10.0 TBD 10 800 /4 output /8 output /12 output /16 output /20 output /24 output /48 output 200.0 100.0 66.6 50.0 40.0 33.3 16.6 0.3 20 1600 400.0 200.0 133.3 100.0 80.0 66.6 33.3 1.3 VCC-0.3 (PCLK) 40 150 100 45 RMS (1 )i RMS (1 ) RMS (1 ) 50 TBD TBD TBD 10 0.05 TBD 55 0.8 TBD 60 Unit MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz V V V % ps ps % ps ps ps kHz ms ns 20% to 80% PLL locked PLL locked Condition PLL locked
Input reference frequency in PLL bypass modec fXTAL fVCO fMAX Crystal interface frequency ranged VCO frequency rangee Output Frequency
PLL bypass
VPP VCMR VO(P-P) frefDC t() tsk(O) DC tJIT(CC) tJIT(PER) tJIT() BW tLOCK tr, tf a. b. c. d. e. f. g.
Differential input voltagef (peak-to-peak) Differential input crosspoint voltageg (PCLK) Differential output voltage (peak-to-peak) Reference Input Duty Cycle Propagation Delay (static phase offset) (PCLK, PCLK to FB_IN) Output-to-output Skewh Output duty cycle Cycle-to-cycle jitter Period Jitter I/O Phase Jitter PLL closed loop bandwidthj Maximum PLL Lock Time Output Rise/Fall Time
h. i. j.
AC characteristics are design targets and pending characterization. AC characteristics apply for parallel output termination of 50 to VTT. In bypass mode, the MPC9992 divides the input reference clock. The crystal frequency range must both meet the interface frequency range and VCO lock range divided by the feedback divider ratio: fXTAL(min, max) = fVCO(min, max) / (M VCO_SEL) and 10 MHz fXTAL 20 MHz. The input reference frequency must match the VCO lock range divided by the total feedback divider ratio: fref = fVCO / (M VCO_SEL) VPP is the minimum differential input voltage swing required to maintain AC characteristics including tpd and device-to-device skew VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR (AC) range and the input swing lies within the VPP (AC) specification. Violation of VCMR (AC) or VPP (AC) impacts the device propagation delay, device and part-to-part skew. See application section for part-to-part skew calculation. See application section for a jitter calculation for other confidence factors than 1 . -3 dB point of PLL transfer characteristics.
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MPC9992
APPLICATIONS INFORMATION
SYNC Output Description The MPC9992 has a system synchronization pulse output QSYNC. In configurations with the output frequency relationships are not integer multiples of each other QSYNC provides a signal for system synchronization purposes. The MPC9992 monitors the relationship between the A bank and the B bank of outputs. The QSYNC output is asserted (logic high) one QA period in duration after the coincident rising edges of the QA and QB outputs. The placement of the pulse is dependent on the QA and QB output frequencies ratio. Table 2 shows the waveforms for the QSYNC output. The QSYNC output is defined for all possible combinations of the bank A and bank B outputs.
1:1 Mode QA
QB QSYNC 2:1 Mode QA VCC
QB
QSYNC 3:1 Mode QA
QB
QSYNC 3:2 Mode QA
QB
QSYNC 4:3 Mode QA
QB
QSYNC
Figure 3. QSYNC Timing Diagram
TIMING SOLUTIONS
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MPC9992
Power Supply Filtering The MPC9992 is a mixed analog/digital product. Its analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. Random noise on the V CC_PLL power supply impacts the device characteristics, for instance I/O jitter. The MPC9992 provides separate power supplies for the output buffers (VCC) and the phase-locked loop (VCC_PLL) of the device. The purpose of this design technique is to isolate the high switching noise digital outputs from the relatively sensitive internal analog phase-locked loop. In a digital system environment where it is more difficult to minimize noise on the power supplies a second level of isolation may be required. The simple but effective form of isolation is a power supply filter on the VCC_PLL pin for the MPC9992. Figure 4. illustrates a typical power supply filter scheme. The MPC9992 frequency and phase stability is most susceptible to noise with spectral content in the 100kHz to 20MHz range. Therefore the filter should be designed to target this range. The key parameter that needs to be met in the final filter design is the DC voltage drop across the series filter resistor RF. From the data sheet the ICC_PLL current (the current sourced through the VCC_PLL pin) is typically 3 mA (5 mA maximum), assuming that a minimum of 2.325V (VCC=3.3V or VCC=2.5V) must be maintained on the VCC_PLL pin. The resistor RF shown in Figure 4. "VCC_PLL Power Supply Filter" must have a resistance of 9-10W (VCC=2.5V) to meet the voltage drop criteria.
RF = 9-10 VCC RF CF 10 nF CF = 22 F VCC_PLL MPC9992 VCC 33...100 nF
Figure 4. VCC_PLL Power Supply Filter The minimum values for RF and the filter capacitor CF are defined by the required filter characteristics: the RC filter should provide an attenuation greater than 40 dB for noise whose spectral content is above 100 kHz. In the example RC filter shown in Figure 4. "VCC_PLL Power Supply Filter", the filter cut-off frequency is around 3-5 kHz and the noise attenuation at 100 kHz is better than 42 dB. As the noise frequency crosses the series resonant point of an individual capacitor its overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the PLL. Although the MPC9992 has several design features to minimize the susceptibility to power supply noise (isolated power and grounds and fully differential PLL) there still may be applications in which overall performance is being degraded due to system power supply noise. The power supply filter schemes discussed in this section should be adequate to eliminate power supply noise related problems in most designs.
Differential Pulse Generator Z = 50 W
Z = 50
Z = 50
RT = 50 VTT
MPC9992 DUT
RT = 50 VTT
Figure 5. MPC9992 AC test reference
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TIMING SOLUTIONS
MPC9992
OUTLINE DIMENSIONS
FA SUFFIX 32 LEAD LQFP PACKAGE CASE 873A-02 ISSUE A
A
32 4X 25
A1
0.20 (0.008) AB T-U Z
1
-T- B B1
8
-U- V P DETAIL Y
17
AE
V1 AE DETAIL Y
9
-Z- 9 S1 S
4X
0.20 (0.008) AC T-U Z
G -AB-
SEATING PLANE
DETAIL AD
-AC-
BASE METAL
N
F
8X
D
M_ R
0.20 (0.008)
M
AC T-U Z
0.10 (0.004) AC
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE -AB- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -T-, -U-, AND -Z- TO BE DETERMINED AT DATUM PLANE -AB-. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -AC-. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -AB-. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.520 (0.020). 8. MINIMUM SOLDER PLATE THICKNESS SHALL BE 0.0076 (0.0003). 9. EXACT SHAPE OF EACH CORNER MAY VARY FROM DEPICTION. MILLIMETERS MIN MAX 7.000 BSC 3.500 BSC 7.000 BSC 3.500 BSC 1.400 1.600 0.300 0.450 1.350 1.450 0.300 0.400 0.800 BSC 0.050 0.150 0.090 0.200 0.500 0.700 12_ REF 0.090 0.160 0.400 BSC 1_ 5_ 0.150 0.250 9.000 BSC 4.500 BSC 9.000 BSC 4.500 BSC 0.200 REF 1.000 REF INCHES MIN MAX 0.276 BSC 0.138 BSC 0.276 BSC 0.138 BSC 0.055 0.063 0.012 0.018 0.053 0.057 0.012 0.016 0.031 BSC 0.002 0.006 0.004 0.008 0.020 0.028 12_ REF 0.004 0.006 0.016 BSC 1_ 5_ 0.006 0.010 0.354 BSC 0.177 BSC 0.354 BSC 0.177 BSC 0.008 REF 0.039 REF
J
CE
SECTION AE-AE
X DETAIL AD
TIMING SOLUTIONS
GAUGE PLANE
0.250 (0.010)
H
W
K
Q_
DIM A A1 B B1 C D E F G H J K M N P Q R S S1 V V1 W X
9
-T-, -U-, -Z- MOTOROLA
EE EE EE
MPC9992
NOTES
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MPC9992
NOTES
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MPC9992
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MPC9992/D TIMING SOLUTIONS

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